It is widely recognized that computer systems anticipated in the 2020 time frame will include many-core processors with 100s of cores per chip, their performance will be driven by parallelism and constrained by energy, data movement and scalability of coherence protocols. Multi-core processors consisting in tens of cores already became mainstream (e.g., Intel Xeon Phi), but they still rely on traditional, inefficient cache coherence protocols.

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The goal of this project is to design a compile-time analysis to statically expose information about the code's characteristics, in particular a classification of memory accesses, in order to design a more efficient cache coherence protocol and attain scalability, performance and energy efficiency.

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The compiler is responsible to identify data-race-free (DRF) regions, and to delineate them from the non-data-race-free (nDRF) regions. The driving force of this classification is that DRF regions can be executed under a relaxed coherence protocol, thus providing efficiency and scalability. Since the classification is performed at compile-time, it is guaranteed throughout the entire execution. Therefore, the design of the protocol is highly simplified, as it does not need to account for misclassifications. The coherence protocol must simply handle DRF regions and nDRF regions accordingly, to achieve maximum efficiency. Moreover, by embedding support for both DRF and nDRF regions, compatibility with legacy software is ensured.

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Given the expertise of both sides, compile-time analysis of memory accesses and designing novel coherence protocols, we are confident that such a collaboration can lead to high-quality publications in the given 4-months time frame.